CSD Internal Exams
Reconfigurable platform and HDL

C 12 Reconfigurable  Platforms and HDL

 

 

Teaching Scheme                                                                                           Examination Scheme

Lectures: 4 Hrs./Week

Credit: 4                                                               

Practical:2Hrs/week

Credit: 1     

Course outcomes

·         To learn different reconfigurable architectures.

·         To be Familiar with SoC, NoC.

·         To be capable of designing and implementing combinational and sequential digital circuits and optimize them with respect to different constraints, such as area, delay, power, or reliability.                                                                

 

Unit 1:

Computing requirements, Area, Technology scaling, Instructions,Custom ComputingMachine,

Overview, Comparison of Computing Machines.

 

Unit 2:

 Interconnects, Requirements, Delays in VLSI Structures; Partitioning and Placement,

Routing; Computing Elements, LUT’s, LUT Mapping,

ALU and CLB’s, Retiming, Fine-grained & Coarse-grained structures; Multicontext;

Comparison of different architectures viz. PDSPs, RALU, VLIW, Vector Processors, Memories,

 

Unit 3:

Arrays for fast computations, CPLDs, FPGAs, Multicontext, Partial Reconfigurable Devices;

TSFPGA, DPGA, Mattrix; Best suitable approach for RD; Case study. Control Logic, Binding

Time and Programming Styles, Overheads, Data Density, Data BW, Function density, Function

diversity, Interconnect methods, Best suitable methods for RD;

 

Unit 4:

Contexts, Context switching; Area calculations for PE;Efficiency, ISP, Hot Reconfiguration;

Case study. Architectures for existing multi FPGA systems, Compilation Techniques

for mapping applications described in a HDL to reconfigurable hardware, Study

of existing reconfigurable computing systems to identify existing system limitations and

to highlight opportunities for research;

 

Unit 5:

Software challenges in System on chip; Testability challenges; Case studies. Modeling,

 

Temporal portioning algorithms, Online temporal placement, Device space management,

 

Unit6:                                                                                                                                             .                                                                                                                                         

Direct communication, Third party communication, Bus based communication,

Circuit switching, Network on chip, Dynamic network on chip, Partial reconfigurable design.

 

References:

1. Andre Dehon, “Reconfigurable Architectures for General Purpose Computing”.

2. IEEE Journal papers on Reconfigurable Architectures.

3. “High Performance Computing Architectures” (HPCA) Society papers.

4. Christophe Bobda, “Introduction to Reconfigurable Computing”, Springer Publication.

5. Maya Gokhale, Paul Ghaham, “Reconfigurable Computing”, Springer Publication.

 

C 12 Reconfigurable  Platforms and HDL

 

 

Teaching Scheme                                                                                           Examination Scheme

Lectures: 4 Hrs./Week

Credit: 4                                                               

Practical:2Hrs/week

Credit: 1     

Course outcomes

·         To learn different reconfigurable architectures.

·         To be Familiar with SoC, NoC.

·        

 

6hrs.

 

 

 

7hrs.

 

 

 

 

 

6hrs.

 

 

 

 

 

7hrs.

 

 

 

 

 

 

6hrs.

 

 

 

 

 

 

 

 

 

 

7hrs.

 
 

To be capable of designing and implementing combinational and sequential digital circuits and optimize them with respect to different constraints, such as area, delay, power, or reliability.                                                                

 

Unit 1:

Computing requirements, Area, Technology scaling, Instructions,Custom ComputingMachine,

Overview, Comparison of Computing Machines.

 

Unit 2:

 Interconnects, Requirements, Delays in VLSI Structures; Partitioning and Placement,

Routing; Computing Elements, LUT’s, LUT Mapping,

ALU and CLB’s, Retiming, Fine-grained & Coarse-grained structures; Multicontext;

Comparison of different architectures viz. PDSPs, RALU, VLIW, Vector Processors, Memories,

 

Unit 3:

Arrays for fast computations, CPLDs, FPGAs, Multicontext, Partial Reconfigurable Devices;

TSFPGA, DPGA, Mattrix; Best suitable approach for RD; Case study. Control Logic, Binding

Time and Programming Styles, Overheads, Data Density, Data BW, Function density, Function

diversity, Interconnect methods, Best suitable methods for RD;

 

Unit 4:

Contexts, Context switching; Area calculations for PE;Efficiency, ISP, Hot Reconfiguration;

Case study. Architectures for existing multi FPGA systems, Compilation Techniques

for mapping applications described in a HDL to reconfigurable hardware, Study

of existing reconfigurable computing systems to identify existing system limitations and

to highlight opportunities for research;

 

Unit 5:

Software challenges in System on chip; Testability challenges; Case studies. Modeling,

 

 

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